The present invention relates to integrated circuit fabrication, and more particularly to a process of fabricating a split-gate flash memory cell, which utilizes self-aligned process to precisely define both channel lengths of the stacked-gate transistor and isolation transistor of a memory cell. As such, better controllability for manufacturing and high operating performance can be obtained.
Split-gate Flash EEPROMs are well-known nonvolatile memory ICs in this art, and have the advantages of preventing the leakage current caused bv an over-erased cell, which increases the cell current drown. One split-gate flash EEPROM structure is disclosed in an article by Gheorghe Samachisa, et al. entitled "A 128K Flash EEPROM Using Double-Polysilicon Technology", published in IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, pp. 676-683, October 1987. This prior split gate structure and its equivalent circuit are shown in FIGS. 1 through 3. FIG. 1 illustrates a schematic layout of a split gate memory cell, FIG. 2 illustrates a cross-section of the memory cell, and FIG. 3 illustrates an equivalent circuit diagram of the memory cell. As shown in FIGS. 1 and 2, a first polysilicon layer 12 acting as the floating gate is formed above a face of a P-type silicon substrate 1. A second polysilicon layer 14 is further deposited and patterned to form the control gate and the word lines in a memory array. A tunnel oxide 11 is formed between the floating gate 12, parts of the control gate 14 and the substrate 1. An interpoly dielectric 13 such as an oxide-nitride-oxide (ONO) structure is formed between the polysilicon gates 12 and 14. The N.sup.+ diffusion region 15 adjacent to the right edge of the floating gate 12 is the drain, and the N.sup.+ diffusion region 16 adjacent to the left edge of the control gate 14 is the source. The memory cell structure can be thought of as two transistors in series, especially referring to FIG. 3. One is a stacked-gate (floating-gate) memory transistor 20, and the other is an isolation transistor 22 which is a simple enhancement transistor controlled by the control gate 14, i.e. the word line. In FIG. 2, "L.sub.1 " indicates the channel length of the memory transistor 20, "L.sub.2 " the channel length of the enhancement transistor 22, and "L" the total channel length of the split gate flash memory cell.
As disclosed in the article, the purpose of the series enhancement transistor 22 in this flash EEPROM cell is to prevent the leakage current in a memory array during programming and/or reading caused by an over-erased cell. More specifically, unlike ultraviolet (UV) light erasing, electrical erasing is not self-limiting. Electrical erasing can (and usually does) leave the floating gate 12 positively charged, thus turning the memory cell 20 into a depletion-mode transistor. The series transistor 22 is needed to prevent current flow under this condition. The extra cell size added by the series enhancement transistor can also improve the cell current and programming characteristics even without considering the benefit of electrical erasability.
Although the split gate flash EEPROM has the above-described advantages, the memory cell structure of FIGS. 1 and 2 still has a drawback. That is, the process of fabricating the memory cell requires the use of photolithography technology to define the channel length L.sub.1 of the memory transistor 20 as well as the channel length l.sub.2 of the isolation transistor 22. Even though the total channel length L=L.sub.1 +L.sub.2 is fixed, the channel lengths L.sub.1 and L.sub.2 must depend on the photolithography alignment between the polysilicon gates 12 and 14. This can lead to difficulty in precise control of the channel lengths L.sub.1 and L.sub.2. Thus, the operating performance of the split-gate flash memory may be significantly affected by processing misalignments.
Another split-gate flash memory cell structure is disclosed in U.S. Pat. No. 4,868,629, issued to B. Eitan on Sep. 19, 1989. FIG. 4 illustrates in cross section the split gate structure of this Patent. As shown in FIG. 4, a tunnel oxide 30 is formed on a P-type silicon substrate 3, and a patterned polycrystalline silicon 32 is formed on the tunnel oxide 30 to act as the floating gate. A photoresist layer 38 is then formed over the top surface of the structure, and is patterned to expose the planned source/drain areas, followed by an ion implantation to dope N.sup.++ source 36 and drain 34 regions. The process of fabricating this split gate structure has the advantage of self-aligning the drain region 34 to one edge of the floating gate 32, but still has the drawback of uncertainty in the channel length of the isolation transistor and thus the total channel length of the memory cell, owing to difficulty in precise alignment of the intermediate photoresist part 38 to the floating gate 32. Thus, the operating performance of this split-gate flash memory may be significantly affected by processing misalignments.